IO cells are semiconductor circuit devices generally embedded in a semiconductor material core, which are designed to send and/or receive binary data signals through a transmission line. By way of examples, IO cells may be used in a system bus for a computer system, or in the various internal busses and system bus interface units within a CPU, or may be stand alone devices on an integrated circuit chip. Additionally, the IO cells can be used to send and receive data between peripherals of a computer system, or through transmission lines connected to routers, servers and other such devices in an electronic communications network.
IO bandwidth is the amount of data that can be transmitted between IO cells in a fixed amount of time. Rapid improvements in integrated circuit technology have imposed ever-increasing requirements for larger IO bandwidth. This is particularly problematic for I/O devices, which must interface with a CPU core. For example, a fast disk drive can be hampered by a bus with low IO bandwidth.
Bi-directional I/O cells are designed to increase 10 bandwidth by reducing the number of wires needed to transmit data by enabling simultaneous transmission of data on the same wire. One such prior art bi-directional I/O cell is described in the article titled “A 900 Mb/s Bi-directional Signaling Scheme”, by Mooney et al., in the IEEE Journal of solid-state Circuits, Vol. 30, No. 12, December 1995 (the Mooney article), which is herein incorporated by reference.
The Mooney article describes the basic theory of bi-directional IO cells in an idealized situation utilizing a single differential amplifier as the receiver of the IO cells. For purposes of clarity, a prior art bi-directional IO cell in accordance with the Mooney article will now be described.
Referring to FIG. 1, an exemplary embodiment of a pair of prior art bi-directional IO cells in accordance with the Mooney article is shown generally at IO. The pair IO includes IO cell 12 (cell A) connected to IO cell 14 (cell B) through a line 16 having a predetermined line impedance of Zo 17. Each IO cell 12 and 14 has an output driver 18 (DRV A) and 20 (DRV B) configured to output data through their respective driver output terminals 22 and 24. The pair of output terminals 22 and 24 is placed on opposite ends of the line 16 at IO ports (or nodes) 26 and 28, and data is transmitted simultaneously in two directions. This theoretically doubles the effective bandwidth per wire without requiring an increase in the bandwidth requirements of the system components.
This scheme takes advantage of the fact that, in an ideally impedance matched system, no reflections or noise occur, and so the bandwidth in the opposite direction of signal flow is available for use. The output impedance of the drivers 18 and 20 are ideally adjusted to match the impedance 17 (Zo) of the line 16 and used as the termination for the driver on the opposite end of the line 16.
Core output signal 30 (COA) from the components (not shown) is electrically connected in series with node 32 and input 34 of driver 18. Core output signal 36 (COB), also from the components, is in series connection with node 38 and tho input 40 of driver 20. Node 32 is also in electrical communication to the select input 42 of reference voltage source 44 (REF A), and node 38 is additionally in electrical communication to the select input 46 of reference voltage source 48 (REF B). Both the REF A and REF B voltage sources have a high voltage level reference output and a low voltage level reference output which are predetermined percentages of the CPU board level power supply voltage Vcc, e.g., in this embodiment ¾ Vcc for the high reference and ¼ Vcc for the low reference. The select inputs 42 and 46 select between the high and low reference voltages of REFA and REFB depending on whether COA and COB are in a high state or low state resectively. The reference voltages are transmitted through thee reference source outputs 50 and 56 respectively. In this way, the reference voltage sources REF A and REF B are dynamically adjustable depending on the state of the core output data COA and COB respectively.
In turn, the output 50 of REF A 44 is connected to the inverting input 52 of a single differential amplifier 54 (DIFF A), and the output 56 of REF B 48 is connected to the inverting input 58 of a single differential amplifier 60 (DIFF B). DIFF A and B are utilized as the receivers for the IO cells 12 and 14 respectively. That is, the non-inverting input 62 of DIFF A receives data transmitted to the IO port 26 from IO cell 14, and the non-inverting input 64 of DIFF B receives data transmitted to IO port 28 from IO cell 12. The output 66 of DIFF A generates the core input data 70 (CIA) for Cell A, and the output 68 of DIFF B generates the core input data 72 (CIB) for Cell B.
Referring to FIGS. 2 and 3, if the transmission line losses are small, e.g., the length of the transmission line 16 is only a few meters, than the COA and COB outputs form a voltage divider circuit as shown generally at 80 in FIG. 2. This voltage divider circuit 80 is used to transmit four binary states on the line 16. These correspond to combinations of the two states of the two drivers 18 and 20. The voltage divider 80 creates an encoding of the four binary states, which are shown in FIG. 3.
This encoded data is decoded by adjusting the threshold of the differential amplifiers, DIFF A and DIFF B, according to the state of the outgoing data. This is the purpose of the reference generators (REFA and REFB). To highlight this process the following four examples cover four data sequences of:    1) COA switching between low and high when COB is in a low state;    2) COA switching between low and high when COB is in a high state;    3) COB switching between low and high when COA is in a low state; and    4) COB switching between low and high when COA is in a high state.
In the first example, consider the data sequence shown in FIG. 4. For purposes of clarity, the data signals are given the same reference numbers and names as the associated hardware, which generates them in FIG. 1. In this example, COB of FIG. 1 is in the low state and COA is switching, i.e., transmitting data. As COA switches between the high and low states, the line voltage moves between ½ Vcc and Vcc, respectively. REFA alternates between ¾ Vcc and ¼ Vcc, while REFB is a constant ¼ Vcc. Note that the line voltage is always lower than REFA, while DIFFB sees a signal with a ½ Vcc swing centered on a ¼ Vcc reference. CIA is, therefore, a constant zero, which reflects the state of COB, while CIB follows COA. REFA switching is used to keep CIA constant as the line voltage switches.
Referring again to FIG. 3, the second example is when COB remains high, i.e., 1, and COA switches from 0 to 1. In this example the line 16 switches from ½ Vcc and Vcc while REF A always remains below the line 16 as it switches from ¼ Vcc to ¾ Vcc. Therefore, the output of DIFFA, i.e., CIA, will remain a constant at 1 following the output of COB. On the other hand, REF B is constant at ¾ Vcc so the output of DIFFF B, i.e., CIB, will swing from 0 to 1 to follow COA.
The third example is when COA remains low, and COB switches from 0 to 1. In that case the line 16 switches from Vss (the system common) to ½ Vcc. REF A remains constant at ¼ Vcc and REF B switches between ¼ Vcc and ¾ Vcc. Since REF B is always above the line 16 signal, CIB will follow COA and remain 0. Since the line will swing above and below REF A, the output of CIA will follow the output of COB and switch from 0 to 1.
In the fourth example, COA remains high, COB switches from 0 to 1, and the line 16 switches from ½ Vcc to Vcc. REF A remains constant at ¾ Vcc and REF B switches between ¼ Vcc and ¾ Vcc. Since REF B is always below the line 16 signal, CIB will follow COA and remain at 1. Since the line will swing above and below REF A, the output of CIA will follow the output of COB and switch from 0 to 1.
In each of the above four examples, it can be seen that CIB is configured to follow the output of COB, and CIA is configured to follow the output of COB. Both drivers 22 and 24 switching is a direct extension of the above four examples with both REFA and RBFB switching to correctly decode the line voltage 16 at the differential amplifiers DIFF A and DIFF B, i.e., the receivers. Dynamically adjusting the receiver threshold reference voltage REF A and REF B allows, in effect, a digital decoding of the line voltage 16. This reduces the susceptibility of the circuit to noise in comparison with analog decoding methods.
In this ideal case (i.e., a loss less line 16, both drivers 18 and 20 ideally matched to the line 16, no noise problems and step function input signals at nodes 26 and 28), the presence of the transmission line 16 does not affect the decoding, since the line 16 is correctly terminated for signals traveling in both directions. The only effect of the line 16 is a time shifting of the edges from and to nodes 26 and 28. In this ideal system, the only voltages seen on the line 16 and at nodes 26 and 28 will be those shown in FIG. 3.
However, switching between voltage references introduce switching errors on the inverting input of each differential amplifier DIFF A and B. These switching errors can get magnified by several orders of magnitude as they pass through the amplifier, making the output signals CIA and CIB unacceptably noisy. This becomes especially problematic when communicating between a pair of devices having many IO cells tied in parallel to reference voltage circuits at the CPU board level. Under those conditions, the switching errors can be transmitted among the IO cells greatly exacerbating the problem.
Additionally, the receiver and reference voltage circuits described in the Mooney article can have noise problems due to several factors. For example, electromagnetic emissions from a variety of internal or external sources, e.g., radio waves, near by electrical wires or bad connections, can produce substantial random noise, i.e., EMI, on the output of the receivers. Also the switching power supplies, which are connected to the reference circuits, can introduce switching noise, i.e., di/dt noise. Common mode noise, i.e., noise signals that are common to both inputs of a power supply or amplifier, can also be a significant factor.
Moreover, noise can be generated from impedance mismatches that may arise at the IO cell termination point (the output drives of the IO cell) as reflected signals arrive during an outbound transition. That is, mismatches in the impedance at the ends of the transmission line can cause output data signals to be reflected back at a natural frequency that is dependent in large part on the length of the transmission line. This natural frequency is not always in phase with the frequency of the output data signals. The switching of output data signals during the transitioning of incoming reflected data signals can create an a lot of noise therefore significantly decreasing the signal to noise ratio in the input and output signals.
Leakage current on the output side of the receivers, i.e., differential amplifiers, can also be a problem. The thickness of both the p and n layers at the p-n junctions of the latest generation differential amplifiers are designed very thin, e.g., only about 10 atoms thick, for high speed switching. However, these thin layers are also prone to leakage currents, which can skew the data signals.
An attempt to minimize some of these problems is disclosed in another prior art bidirectional IO cell design described in the article titled “3.2 GHz 6.4 Gb/s per Wire Signaling in 0.18 micro meter CMOS, by M. Haycock and R Mooney, published in the Digest of Technical Papers presented in the IEEE International Solid-State Circuits Conference, Feb. 5-6 2001, pages 62-63 and 430, ISSN: 0193-6530 (the Haycock article), which is herein incorporated by reference. This article describes a bidirectional IO cell having a variable output slew rate, which can limit the frequency content on the link between IO cells, reduce the di/dt noise during switching, and mitigate the effects of impedance discontinuities.
However, the variable output slew rate is a relatively complex circuit that increases chip space and increases cost. Additionally, inherent problems due to random EMI noise, di/dt noise, common mode noise, leakage currents and impedance mismatches still exist for the circuit described in the Haycock article. Moreover, the errors introduced by switching between reference voltage levels on the input of the differential amplifier receivers is not addressed in the Haycock article.
Based on the foregoing, it is the general object of the present invention to provide a signal conditioning circuit for a bi-directional IO cell that overcomes the problems and drawbacks associated with prior bi-directional IO cells.